I believe it should still look like this. Using this terminology, Alder Lake has a memory controller with a width of 128bit, just like all prior mainstream platforms (2×64 bits with DDR4 and 4×32 bits with DDR5). Perhaps the ideal way to handle this would be to start to state the controller width, instead of the number of channels, as is done with GPU. You might therefore find the same Alder Lake setup is sometimes given the dual-channel label as well as the quad-channel label (e.g. This might cause confusion, perhaps it might be better to keep referring to this setup as two channels. So despite the theoretical bandwidth not being changed, it becomes possible to yield a higher practically achievable bandwidth and thereby a higher performance out of that same theoretical potential. With two modules you therefore have four logical channels with 32bit width each.įrom the point of view of the theoretical bandwidth there is no actual change, the benefit of two “pseudo channels” within a single module rests on their ability to support two independent accesses at the same time. While in the case of DDR4 a single module behaves as a single 64bit channel, in the case of DDR5 a change has been conducted whereby a module has been split into two 32bit channels.
Such reporting is not incorrect, because every DDR5 module behaves as two independent channels (or logical channels) from the perspective of the memory controller. Until now, this has been the privilege of Threadrippers or Intel X99/X299 platforms and similar hardware. One of the first things you might encounter with Alder Lake is that CPU-Z will indicate that you have a four channel memory controller („Quad Channel“).
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